AMD Unveils FinFET based GCN Optimization with Double the Energy Efficiency and HBM

AMD is currently doing its live analysts day webcast and have unveiled their new GCN revision which will feature some interesting features. Graphics Cadre Next is AMD's mod GPU architecture that was launched back in 2022. This particular revision of GCN is basically an implementation that will be based (and optimized for) FinFET procedure applied science and volition roughly double the power efficiency of the architecture. At the same time, HBM fabricated an appearance too.

A slide from the Analysts Day webcast showing the upcoming Radeon 300 Series products.

AMD ups energy efficiency with GCN Optimization and reiterates HBM (retentivity)

AMD'due south analysts day spider web cast revealed quite a few bits of interesting data nigh AMD's various IPs. One of the more than relevant updates was the conversation of GCN based on xiv/16nm FinFET and High Bandwidth Memory. CEO Lisa Su made it clear that today was non a product launch - it was more of a tech confirmation of what will be included in the upcoming flagship GPUs. Basically, sub 20nm node (for 2022), HBM retentivity and 1 helluva launch are all that take been confirmed. Given below is the slide catch from the analyst effect which shows Graphic Core Next (GCN)'s development throughout its launch to date.

Sadly, the slide doesn't really reveal alot except confirming the fact that AMD will be shifting to FinFET with their side by side flagship and the fact that information technology will have roughly twice the free energy efficiency of a planar dice. Lisa Su mentioned that the new architecture would be launching along with the flagship Radeon 300 Series products old in the electric current quarter, in the coming weeks (think Computex). Therefore, information is deliberately lacking in this consequence, just hey, all this rumor-confirmation really helps us slumber at night.

Up side by side is AMD re-stating facts almost HBM (and too confirming its use in its side by side flagship). Nosotros already know quite a lot about HBM. Nosotros know that HBM1 is limited to 4GB but with a Dual Link Interposing design, SK Hynix will exist able to stack 4x (Dual 1GB HBM modules) via an Interposer (2.5D stacking). The blueprint will have very loftier performance at low clock speeds and will as well be very power efficient as compared to GDDR5.

2x four-HI HBM1 (which should technically be called 8-Hi-Hello co-ordinate to nomenclature rules) features a 1024-bit interface, two prefetch operations per IO (dual command) and can push 128GB per 2nd per pin. The tRC is 48nm, tCCD is 2ns (1tCK), and VDD is one.2V. The four-Hullo HBM2 (generation 2) features a 1024 bit interface, two prefetch operations per IO (dual control), 64 Byte access granularity (=I/O x prefetch) and can push 256 GB per 2d per pin.

The bandwidth of an HBM equipped card will almost probably exist either 512 GB/s – 1024 GB/s depending on the combination used. two.5D is the best selection for high performance ASICs currently primarily because 3D stacking would result in a very very bad oestrus direction. Since the memory would be stacked on top of the die, it would become very difficult to control the oestrus produced from the power hungry chips that are mod GPUs. Needless to say, this generation of GPUs but got very exciting and AMD's HBM memory appears to be on the cutting edge of Industry technology.

Source: https://wccftech.com/amd-finfet-gcn-graphic-core-next-hbm-power-efficiency/

Posted by: dunlapsuposincer.blogspot.com

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